Projects by Veryl — FLOSS/Fund

Veryl Veryl (1 project)

A hardware description language that compiles to SystemVerilog, with an optimized syntax, interoperability with SystemVerilog, and a productive toolchain including a compiler, formatter, linter, la...

MIT +1 hardware, hdl, systemverilog, fpga, asic, compiler, programming-language, developer-tools

Mon, 28 Sep 2026 12:00:05 UTC

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Veryl